This invention is in the field of integrated circuits, and is more specifically directed to clock synthesis circuits for generating periodic signals at selected frequencies for use in integrated circuits.
As is fundamental in the art, many modem electronic systems now include numerous integrated circuits that operate in conjunction with one another. In complex high performance systems such as modern personal computers and workstations, these integrated circuits are synchronized with a system clock. In consumer-oriented systems such as televisions and home theaters, for example, system operation is synchronized with respect to a synchronization pulse that is included within the display signal itself. Modern spread-spectrum communications transmitters and receivers require the generation of high-frequency clock signals for the modulation and demodulation, respectively, of signals over the multiple subchannels of the spread spectrum bandwidth. In these and other electronic systems, the generation of periodic signals for clocking the operation of circuit functions based upon a system clock or synchronization pulse, is a common and often critical function.
A conventional approach for generating periodic signals based upon a reference clock utilizes the well-known phase-locked loop, or PLL. In general, PLL circuits operate by comparing the time at which an edge of a reference clock is received relative to a corresponding edge of an internally generated clock. If a significant delay between these two edges is detected, the generation of the internal clock is adjusted to more closely match the received reference clock. In conventional analog PLLs, the frequency of a voltage controlled oscillator is adjusted by a filtered signal from a phase detector that compares system and chip clocks, so that the instantaneous frequency of the internal chip clock is advanced or retarded depending upon whether the chip clock lags or leads the system clock. Analog PLLs therefore adjust the phase of the chip clock in a substantially continuous manner in response to a phase difference between the internal chip clock and the system clock. This smooth operation generally depends upon the filtering of the output of the phase detector circuit, but can be made quite well-behaved in most implementations. Additionally, by inserting frequency dividers in the forward and feedback loops, analog PLLs can be used to generate periodic signals of a selectable frequency multiple of the input reference clock.
Modern digital integrated circuits generally use digital circuitry to generate multiple internal chip clocks that are based upon the output of a PLL. However, these digitally-generated clock signals can only be adjusted to a discrete accuracy that corresponds to the minimum step size of the digital clock generation circuitry. This incremental change in phase is often noticeable, particularly at high frequencies. The resulting “phase jitter” is now a commonly specified parameter for digital clock circuitry, as this effect is often a limiting factor in the accuracy and performance of the circuit.
Known clock generator circuits based on a phase-locked loop (PLL) are described in Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, June, 2000), pp. 835–46, and in U.S. Pat. No. 6,329,850 B1, issued Dec. 11, 2001 and commonly assigned herewith, both documents incorporated herein by this reference. In these “flying-adder” clock generation circuits, the voltage controlled oscillator (VCO) of the PLL produces a plurality of evenly-spaced output phases at a frequency that is locked to a reference clock. A register stores a digital value that selects the desired phase to be applied to the clock input of a toggle flip-flop from which the output clock is generated. A frequency synthesis circuit adds integer and fraction portions of an incoming frequency selection value to the current contents of the register. The fraction portion of the frequency selection value permits a time-averaged clock frequency to be produced with more precision than would be attained by the integer portions selecting the multiple VCO output phases. This article and U.S. Patent also describe alternative realizations, including multiple frequency synthesis circuits based upon the same PLL and the generation of a phase-shifted secondary output from a phase synthesis circuit that is slaved to the frequency synthesis circuit. Additional performance is obtained by providing separate paths for producing the leading and trailing edges of the output clock.
FIG. 1 illustrates an example of one of the frequency synthesis circuits described in the Mair and Xiu article. In FIG. 1, clock generation circuit 122 includes PLL 125, frequency synthesis circuit 127 for generating a clock signal on line COUT that is at a selected frequency, and phase synthesis circuit 129 for generating a second clock signal on line CSHOUT that is in a fixed phase relationship, and identical frequency, with the clock signal on line COUT. In frequency synthesis circuit 127, thirty-two equally spaced clock phases generated by a VCO in PLL 125 are received at inputs of multiplexer 134. The selected one of the clock phases indicated by select lines SEL appears at the output of multiplexer 134 and is applied to the clock input of D-type flip-flop 136, which is connected in toggle fashion. This inverting output of flip-flop 136 drives the output clock signal on line COUT.
The selection of clock phases by multiplexer 134 according to this preferred embodiment of the invention is determined by an input value presented on lines FREQ, which include both an integer portion and a fractional portion, and is applied to one input of adder 138. The integer portion has a number of bits corresponding to the number of select lines SEL, and thus corresponding to the number of clock phases output by PLL 125. The fractional portion provides additional resolution in the selection of the time-averaged frequency of the output clock signal on line COUT. Adder 138 adds the digital value on lines FREQ with a feedback value from the current output of register 140, and applies this sum to register 140, which is clocked by the output of multiplexer 134. The output of the integer portion of register 140 drives lines SEL applied to multiplexer 134, while the outputs of the integer register and the fraction register of register 140 are together combined into a ten-bit value that is applied back to adder 138 as feedback. In this way, adder 138 adds the current contents of register 140, which includes the current phase selection state applied to multiplexer 134 on lines SEL, to the frequency selection value on lines FREQ, for use in the selection of the next clock phase.
Phase synthesis circuit 129 includes multiplexer 144 which receives the multiple phases generated by PLL 125, and forwards a phase, selected by the digital value on lines SELPH, to the clock input of D-type flip-flop 146. The D input of flip-flop 146 receives the non-inverting output of flip-flop 136 in frequency synthesis circuit 127, and generates the output clock signal on line CSHOUT from its inverting output. Lines SELPH are generated from register 143, which receives a value from adder 142 corresponding to the sum of the current value of lines SEL of frequency synthesis circuit 127 and a digital input value presented on lines PHASE from control circuitry elsewhere within the device.
In operation, the digital value on lines FREQ thus corresponds to the number of phases output from PLL 125 that are to elapse between successive edges of the output clock signal on line COUT. The fractional component of this value provides additional precision in the average output frequency, because these fractional values accumulate and carry in such a manner as to modulate the integer output on lines SEL, and thus modulate the position of the clock edges selected by multiplexer 134. The digital value on lines PHASE indicating the desired phase relationship between the clock signals on lines COUT, CSHOUT is added by adder 142 with the current value of the phase presented on lines SEL; the resulting sum is stored in register 143 and is presented to multiplexer 144 on lines SELPH. Multiplexer 144 then selects the corresponding phase from PLL 125 for application to the clock input of flip-flop 146. Upon the rising transition of this selected clock phase, flip-flop 146 stores the current contents of flip-flop 136 (non-inverted) and applies this state at its inverting output on line CSHOUT.
The Mair and Xiu article and the above-referenced U.S. Pat. No. 6,329,850 B1 each also describe another implementation of a frequency synthesis circuit in which the clock signal is generated in a pipelined manner, by way of separate paths for generating leading and trailing edges of the output clock signal. Each of the paths in this example includes a multiplexer for selecting one of the equally-spaced clock phases output by the voltage controlled oscillator (VCO) in a conventional phase-locked loop (PLL). Logic circuitry at the output of each of the multiplexers are interlocked so that one of the multiplexers drives the output clock leading edge, and the other drives the trailing edge. By providing two separate paths, each path is permitted time to perform the necessary operations to generate its next edge during such time as the other clock edge is being generated by the other path. Specifically, during such time as the rising edge of the output clock is being generated through one path, the other path is updating the value to be applied to its multiplexer to select the output phase for its next edge.
The circuits of the Mair and Xiu article and U.S. Pat. No. 6,329,850 B1, provide important improvements in the generation of clock signals in integrated circuits, including precise selection of clock frequencies with minimal drift, with performance suitable for applications requiring extremely high frequency accuracy. However, certain limitations are present in these circuits. For example, not all possible phase shifts are available for all clock edges, because of the propagation delay through the selection circuitry. Furthermore, these circuits must operate according to various timing constraints.
By way of further background, our copending application Ser. No. 10/026,489, filed Dec. 24, 2001, describes improved clock generation circuits based on the “flying-adder” architecture of the Mair and Xiu article and U.S. Pat. No. 6,329,850 B1. In particular, this copending application describes a clock generation circuit in which two or more frequency synthesis paths terminate at the inputs of a multiplexer, the output of which toggles a toggle mode bistable multivibrator (T flip-flop). Sequential selection of the synthesis paths is controlled in a synchronized manner with the output of the circuit, so that the synthesis path outputs sequentially toggle the flip-flop. In this way, the number of synthesis paths can be increased arbitrarily, with the scaling limited by the performance of control circuits for the output multiplexer. The propagation delay paths of each synthesis path can then extend to the multiple periods of the output clock, making higher output frequency possible. In addition, the toggle signal operates as a double-frequency clock signal.
Each of these conventional circuits are vulnerable to jitter, however. The jitter in the output clock is produced at those cycles in which the sum or sums applied to the select multiplexers vary from one cycle to the next. In the case of FIG. 1, by way of example, jitter is caused by the generation of a carry from the fraction portion of the sum produced by adder 138 and forwarded through register 140 to select lines SEL applied to multiplexer 134. For example, if the frequency select signal is 5.25 (i.e., an average of 5.25 clock phases between adjacent edges), the integer result will increment by five in three out of four cycles, and by six in the fourth cycle. The count of phases between successive clock edges selected by multiplexer 134 will vary in this same manner, causing jitter in the output clock.